Features A Methodology for Comprehensive Schedule Delay Estimation during Design space Exploration in Architectural Synthesis

This letter presents a novel improved delay estimation methodology during scheduling in high level synthesis (HLS) for application specific computing. In general during delay estimation from scheduling during HLS, only functional unit delay is considered. However for current generation of complex digital systems, interconnects (switching elements) also play a very vital role in effective delay evaluation. Thus consideration of interconnect/storage delay during delay estimation from scheduling during HLS becomes very significant, as inaccurate delay estimation inevitably misguides the exploration process during HLS. Motivating from this fact, this letter proposes an improved schedule delay estimation methodology divided into two phases: (a) process of identifying the operations that contribute to the effective delay of the operation chaining based scheduling (b) process of estimating schedule delay considering delay of interconnect (multiplexer unit) and storage elements (latches and final output register) besides regular functional units (FU). The proposed approach more comprehensively estimates the schedule delay than existing practice. Our results on various benchmarks confirm that proposed approach yields estimated delay more comprehensively (reported later) than current standard practice.